//fifo_rd模块
module fifo_rd(
	input				sys_clk		,
	input				sys_rst_n	,
	
	input				rdempty		,	//读空信号
	input				rdfull		,	//读满信号
	input	[7:0]		data		,	//读数据
	output	reg			rdreq		,	//读请求
	);

reg	[7:0]				data_fifo	;	//读取的FIFO数据
reg	[1:0]				flow_cnt	;	//状态流转计数

always	@(posedge sys_clk or negedge sys_rst_n) begin
	if(!sys_rst_n)	begin
		flow_cnt	<= 2'b0;
		data 		<= 8'b0;
		data_fifo	<= 8'b0;
		rdreq		<= 1'b0;
	end	
	else begin
		case(flow_cnt)
			2'd0:	begin
				if(rdfull)	begin
					rdreq <= 1'b1;
					flow_cnt <= flow_cnt + 1'b1;
				end
				else
				flow_cnt <= flow_cnt;
			end
			2'd1:	begin
				if(rdempty)	begin
					data_fifo <= 8'b0;
					rdreq <= 1'b0;
					flow_cnt <= 2'b0;
				end
				else	begin
					data_fifo <= data;
					rdreq <= 1'b1;
				end
			end
			default: flow_cnt <= 2'b0;
		endcase
	end
end

endmodule